74ls112 dip ic

🔹 74LS112 DIP IC – Dual J-K Negative-Edge Triggered Flip-Flop (SN74LS112AN)

The SN74LS112AN is a dual J-K flip-flop IC featuring individual J, K, Clock, Set, and Reset inputs. Output state changes are initiated by the HIGH-to-LOW transition of the clock pulse, and the LOW-level Set and Reset inputs allow asynchronous control regardless of other inputs .

✅ Specifications:

Logic Family: 74LS (Low-Power Schottky TTL)

Package: 16-pin DIP (PDIP)

Supply Voltage: 4.75V – 5.25V

Clock Frequency: 45 MHz (typical max)

Propagation Delay: 20 ns @ 5V, 15pF

Trigger Type: Negative Edge

Output Current: 8mA (Low), -400µA (High)

Operating Temperature: 0°C to +70°C

📦 Features:
✔️ Dual independent J-K flip-flops in one package
✔️ Asynchronous Preset and Clear inputs
✔️ Toggle mode by tying J and K HIGH
✔️ Fully buffered inputs for isolation from external disturbance
✔️ Complementary Q and Q̅ outputs

📦 Applications:
✔️ Counters and frequency dividers
✔️ Shift registers and data storage
✔️ Toggle flip-flop circuits
✔️ Sequential logic and state machines
✔️ Digital control systems