The 74LS73 designed as a dual in-line positive pulse triggered JK flip flop IC. It’s made up of two J-K flip-flops, each with its own J-K, clock, and direct clear inputs. After a complete clock pulse, the flip-flops process the J and K data. The slave is segregated from the master when the clock is low. The data from the J and K inputs is sent to the master on the clock’s positive transition. The J and K inputs are disabled when the clock is high.

• Dual J-K Flip-Flop
• Clock Frequency: 30MHz
• High-level input voltage: 2V
• Low-level input voltage: 0.8V
• Short circuit output current: -100mA
• No. of Flip Flops: 2
• Input clamp voltage: -1.5V
• Propagation delay time: 20ns
• Package: DIP-16